Terabyte Interconnection and Package Laboratory

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 Recent Updates at Teralab

ICML 2023 Acceptance

Ph.D student, Haeyeon Kim's first authored paper "DevFormer: A Symmetric Transformer for Context-Award Device Placement" got accepted to ICML 2023.

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KAIST Cross-Generation Collaborative Lab

Opening ceremony for KAIST cross-generation collaborative lab was held on January 12, 2022. 

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DesignCon 2022 Best Paper Awards

Four Ph.D students, Seongguk Kim, Taein Shin, Seonguk Choi, and Haeyeon Kim, received Best Paper Awards on Feburary 1st, 2023.

IEEE EDAPS 2022 Best Poster Award

Hyunwoo Kim, a master student, received Best Poster Paper Award.

IEEE EPEPS 2022 Best Poster Award

Doctor Hyunwook Park received Best Poster Award.

Teralab Missouri S&T and Georgia Tech Visiting Seminar 2022

KAIST & SK Hynix Invited Seminar on AI-based Design 2022

KAIST & SK Hynix Technical Workshop 2020

Teralab Silicon Valley Visiting Seminar 2019

KAIST & Samsung Technical Workshop 2019

Teralab Silicon Valley Visiting Seminar 2018

 Teralab Graduates in Silicon Valley & the U.S.

*Last updated in March 2023 

Teralab Research Overview

Core Research Fields at Teralab: 5I (SI, PI, TI, EMI, AI)

  Signal and Power Integrity

  Generative and Reinforcement Learning Models

AI-based Package and Interconnect Design Optimization

< AI-X Architect for AI Engineering >

Ref) Jihun Kim, Teralab

< RL-Based Various Package and Interconnect Design Area within HBM Package >

Ref) Jihun Kim, Teralab

< Schemetic diagram of RL-X Architect for SI/PI Design >

Ref) Hyunwook Park, Teralab

(a) Proposed sequential policy-based PEQ optimization for memory channel of HBM using advantage actor-critic (A2C)

(b) Physical dimensions of PEQ in memory channel of HBM

(c) Result of eye-diagram with each optimization method for a random test case

< DRL-based passive equalizer (PEQ) optimization method for high bandwidth memory (HBM) >

Ref) Seonguk Choi, Teralab

(a) Decap Placement Problem (DPP) on Hierarchical PDN

(b) A Novel Device Transformer (DevFormer) Structure

< Imitation Learning and DevFormer-based Optimal Decoupling Capacitor Placement on Power Distribution Network >

Ref) Haeyeon Kim, Teralab

(a) Signal degradation of high-speed memory channel in HBM 

(b) Process of eye diagram generation of GAN model 

(c) Various key parameters driven from the generated eye diagram 

(d) Model architecture of Pix2Pix-based GAN for Eye Diagram Estimation 

< Generative Adversarial Network (GAN) based Eye Diagram Estimation for Design of High Bandwidth Memory (HBM) Interposer Considering Signal Integrity >

Ref) Junghyun Lee, Teralab

Teralab HBM 2.5D/3D Integration Research Roadmap

< High-Bandwidth Memory(HBM) Integrated in 2.5D Interposer Package > 

< Improvements in HBM Technology Over Time >

Ref) Haeyeon Kim, Teralab

< Teralab HBM 2.5/3D Integration Research Roadmap >

Ref) Kyungjun Cho, Teralab

Teralab HBM Packaging-Based Research 

< Signal Integrity Design Considerations in High Bandwidth Memory (HBM) Interposer >

Ref) Kyungjun Cho, Teralab

< Power Integrity Design Considerations in High Bandwidth Memory (HBM) Interposer >

Ref) Kyungjun Cho, Teralab

< Thermal Transmission Line(TTL) and Fluidic Through Silicon Via(F-TSV) based Embedded Cooling Structure for Next-Generation HBM Module >

Ref) Keeyoung Son, Teralab

Teralab Post-HBM Packaging-Based Research

< Near-Memory Computing HBM (NMC-HBM) Architecture for Energy-Efficient and High Performance Computing >

Ref) Seongguk Kim, Teralab

< Proposed Novel 3D Heterogeneous Integration-based Near-Memory-Computing Architecture on HBM for Large-scale AI >

Ref) Jiwon Yoon, Teralab

< Proposed Novel 3D GPU Architecture with L3 Cache DRAM Die Stacked >

Ref) Hyunah Park and Haeseok Suh, Teralab

< Proposed Novel 3D SoC Architecture with Multiple NPUs Stacked >

Ref) Taesoo Kim and Jungmin Ahn, Teralab

< Memory-Centric Computing Architecture with Memory Coherent Interface >

Ref) Jiwon Yoon, Teralab

< Large-scale Chiplet Package on RDL Interposer with Local Silicon Bridge >

Ref) Jihun Kim, Teralab

Full Wafer Scale Chip (FWSC)

< Specification of FWSC, WSE-2 of Cerebras >

Ref) Hyunwoo Kim, Teralab

< Cross-section view of the proposed hierarchical PDN structure for FWSC package >

Ref) Hyunwoo Kim, Teralab

Any Questions?

Please contact our lab representative Keeyoung Son 

E-mail: keeyoung@kaist.ac.kr