Terabyte Interconnection and Package Laboratory

We love wave, that is how we can compute artificial intelligence!

개별연구생 엄현서 피아노 연주회.mp4

AIVA for Piano Solo, Op.11: Rhapsody, composed by AI, played by Teralab undergraduate student, Hyunseo Uhm

Click to find out more about us!

TeraLab Introduction_2023_7.pdf
MCC_HCC_Seminar.pdf
TeraLab Ranings in Research Areas_By Microsoft Academics_2020_5_30.pdf
TeraLab Ranings in Research Areas_By Microsoft Academics_2021_10.pdf
김정호 교수님 연구실 HBM, TSV 관련 저널, 논문, List, 편수, 책 커버, 학위논문 통계.pdf

 Recent Updates at Teralab

DesignCon 2025 Acceptance

Four papers by Dr. Taein Shin, Ph.D students Keeyoung Son, Haeyeon Kim, and a master student, Hyunjun An, got accepted to DesignCon 2025. 

IEEE EPEPS 2024 Acceptance

9 papers by Dr. Taein Shin, Ph.D students, Keunwoo Kim, Keeyoung Son, Haeyeon Kim, Junghyun Lee, and master students, Hyunah Park, Haeseok Suh, Jungmin Ahn and Huynjun An, got accepted to EPEPS 2023.

Naver-Intel-KAIST AI Research Center

NIK AI research center kick-off workshop held in Daejeon on July 4, 2024. 

ICML 2023 Acceptance

Ph.D student, Haeyeon Kim's first authored paper "DevFormer: A Symmetric Transformer for Context-Award Device Placement" got accepted to ICML 2023.

Click above image to read more

KAIST Cross-Generation Collaborative Lab

Opening ceremony for KAIST cross-generation collaborative lab was held on January 12, 2022. 

Click above image to read more

DesignCon 2022 Best Paper Awards

Four Ph.D students, Seongguk Kim, Taein Shin, Seonguk Choi, and Haeyeon Kim, received Best Paper Awards on Feburary 1st, 2023.

IEEE EDAPS 2022 Best Poster Award

Hyunwoo Kim, a master student, received Best Poster Paper Award.


IEEE EPEPS 2022 Best Poster Award

Doctor Hyunwook Park received Best Poster Award.


Teralab Missouri S&T and Georgia Tech Visiting Seminar 2022

KAIST & SK Hynix Invited Seminar on AI-based Design 2022

KAIST & SK Hynix Technical Workshop 2020

Teralab Silicon Valley Visiting Seminar 2019

KAIST & Samsung Technical Workshop 2019

Teralab Silicon Valley Visiting Seminar 2018

 Teralab Graduates in Silicon Valley & the U.S.

*Last updated in March 2023 

Teralab Research Overview

Core Research Fields at Teralab: 5I (SI, PI, TI, EMI, AI)

Teralab Design Innovations: 5 Is

Artificial Intelligence (AI) World Design

AI-X Architect for Engineering Problems

< AI-X Architect for AI Engineering >

Ref) Jihun Kim, Teralab

Generative AI-based Package and Interconnect Design Optimization

< Adaptive Gramian-Angular-Field Segmentation Integration Based Generative Adversarial Network (AGSI-GAN) for HBM I/O Design >

Ref) Junghyun Lee, Teralab

< AGSI-GAN Framework for Accurate Eye Diagram Estimation >

Ref) Junghyun Lee, Teralab

< Overview of Diffusion Rewarded Generative Flow Network (DRGF Net) based TSV array placement in next generation HBM >

Ref) Hyunjun Ahn, Teralab

 < Structure of Diffusion Model for Reward Estimation System >

Ref) Hyunjun Ahn, Teralab

(a) Signal degradation of high-speed memory channel in HBM 

(b) Process of eye diagram generation of GAN model 

(c) Various key parameters driven from the generated eye diagram 

(d) Model architecture of Pix2Pix-based GAN for Eye Diagram Estimation 

< Generative Adversarial Network (GAN) based Eye Diagram Estimation for Design of High Bandwidth Memory (HBM) Interposer Considering Signal Integrity >

Ref) Junghyun Lee, Teralab

Explainable AI-based Package and Interconnect Design Optimization

< XRL-based Decoupling Capacitor Placement using GPT-based Explanation Generator for HBM >

Ref) Keunwoo Kim, Teralab

< Explanation using GPT-based Explanation Generator >

Ref) Keunwoo Kim, Teralab

DRL-based Package and Interconnect Design Optimization

< RL-Based Various Package and Interconnect Design Area within HBM Package >

Ref) Jihun Kim, Teralab

< Schemetic diagram of RL-X Architect for SI/PI Design >

Ref) Hyunwook Park, Teralab

(a) Proposed sequential policy-based PEQ optimization for memory channel of HBM using advantage actor-critic (A2C)

(b) Physical dimensions of PEQ in memory channel of HBM

(c) Result of eye-diagram with each optimization method for a random test case

< DRL-based passive equalizer (PEQ) optimization method for high bandwidth memory (HBM) >

Ref) Seonguk Choi, Teralab

(a) Decap Placement Problem (DPP) on Hierarchical PDN

(b) A Novel Device Transformer (DevFormer) Structure

< Imitation Learning and DevFormer-based Optimal Decoupling Capacitor Placement on Power Distribution Network >

Ref) Haeyeon Kim, Teralab

Teralab HBM 2.5D/3D Integration Research Roadmap

< High-Bandwidth Memory(HBM) Integrated in 2.5D Interposer Package > 

< Improvements in HBM Technology Over Time >

Ref) Haeyeon Kim, Teralab

< Teralab HBM 2.5/3D Integration Research Roadmap >

Ref) Kyungjun Cho, Teralab

Teralab HBM Packaging-Based Research 

< Signal Integrity Design Considerations in High Bandwidth Memory (HBM) Interposer >

Ref) Kyungjun Cho, Teralab

< Power Integrity Design Considerations in High Bandwidth Memory (HBM) Interposer >

Ref) Kyungjun Cho, Teralab

< Thermal Transmission Line(TTL) and Fluidic Through Silicon Via(F-TSV) based Embedded Cooling Structure for Next-Generation HBM Module >

Ref) Keeyoung Son, Teralab

Teralab Next Generation HBM Packaging-Based Research

< Near-Memory Computing HBM (NMC-HBM) Architecture for Energy-Efficient and High Performance Computing >

Ref) Seongguk Kim, Teralab

< Proposed Novel 3D Heterogeneous Integration-based Near-Memory-Computing Architecture on HBM for Large-scale AI >

Ref) Jiwon Yoon, Teralab

< Twin-Tower High Bandwidth Memory (HBM) with Near Memory Computing (NMC) Architecture for Generative Artificial Intelligence  >

Ref) Taesoo Kim, Teralab

< L3 Cache Embedded GPU-High Bandwidth Memory
(L3E-GPU-HBM) Interposer Architecture for Large Language Model (LLM) >

Ref) Haeseok Suh, Teralab

< Level 3(L3) cache stacked GPU architecture with high bandwidth memory(HBM) for high performance in large language models(LLMs) >

Ref) Hyunah Park, Teralab 

< 3D Stacked Neural Processing Unit-System on Chip  (NPU-SoC) Architecture for Generative Artificial Intelligence >

Ref) Taesoo Kim, Teralab 

< 3-Dimensional (3D) System on Chip - Neural Processing Unit (SoC - NPU) Architecture for High Performance Computing (HPC) for Generative Artificial Intelligence (GAI) >

Ref) Jungmin Ahn, Teralab

< Memory-Centric Computing Architecture with Memory Coherent Interface >

Ref) Jiwon Yoon, Teralab

< Large-scale Chiplet Package on RDL Interposer with Local Silicon Bridge >

Ref) Jihun Kim, Teralab

Full Wafer Scale Chip (FWSC)

< Specification of FWSC, WSE-2 of Cerebras >

Ref) Hyunwoo Kim, Teralab

< Cross-section view of the proposed hierarchical PDN structure for FWSC package >

Ref) Hyunwoo Kim, Teralab

Any Questions?

Please contact our lab representative Seonguk Choi

E-mail: seonguk@kaist.ac.kr