< AI-X Architect for AI Engineering >

Ref) Jihun Kim, Teralab

< Adaptive Gramian-Angular-Field Segmentation Integration Based Generative Adversarial Network (AGSI-GAN) for HBM I/O Design >

Ref) Junghyun Lee, Teralab

< AGSI-GAN Framework for Accurate Eye Diagram Estimation >

Ref) Junghyun Lee, Teralab

< Overview of Diffusion Rewarded Generative Flow Network (DRGF Net) based TSV array placement in next generation HBM >

Ref) Hyunjun Ahn, Teralab

 < Structure of Diffusion Model for Reward Estimation System >

Ref) Hyunjun Ahn, Teralab

(a) Signal degradation of high-speed memory channel in HBM 

(d) Model architecture of Pix2Pix-based GAN for Eye Diagram Estimation 

< Generative Adversarial Network (GAN) based Eye Diagram Estimation for Design of High Bandwidth Memory (HBM) Interposer Considering Signal Integrity >

Ref) Junghyun Lee, Teralab

< XRL-based Decoupling Capacitor Placement using GPT-based Explanation Generator for HBM >

Ref) Keunwoo Kim, Teralab

< Explanation using GPT-based Explanation Generator >

Ref) Keunwoo Kim, Teralab

< RL-Based Various Package and Interconnect Design Area within HBM Package >

Ref) Jihun Kim, Teralab

< Schemetic diagram of RL-X Architect for SI/PI Design >

Ref) Hyunwook Park, Teralab

(c) Result of eye-diagram with each optimization method for a random test case

< DRL-based passive equalizer (PEQ) optimization method for high bandwidth memory (HBM) >

Ref) Seonguk Choi, Teralab

(b) A Novel Device Transformer (DevFormer) Structure

< Imitation Learning and DevFormer-based Optimal Decoupling Capacitor Placement on Power Distribution Network >

Ref) Haeyeon Kim, Teralab

< High-Bandwidth Memory(HBM) Integrated in 2.5D Interposer Package > 

< Improvements in HBM Technology Over Time >

Ref) Haeyeon Kim, Teralab

< Teralab HBM 2.5/3D Integration Research Roadmap >

Ref) Kyungjun Cho, Teralab

< Signal Integrity Design Considerations in High Bandwidth Memory (HBM) Interposer >

Ref) Kyungjun Cho, Teralab

< Power Integrity Design Considerations in High Bandwidth Memory (HBM) Interposer >

Ref) Kyungjun Cho, Teralab

< Thermal Transmission Line(TTL) and Fluidic Through Silicon Via(F-TSV) based Embedded Cooling Structure for Next-Generation HBM Module >

Ref) Keeyoung Son, Teralab

< Near-Memory Computing HBM (NMC-HBM) Architecture for Energy-Efficient and High Performance Computing >

Ref) Seongguk Kim, Teralab

< Proposed Novel 3D Heterogeneous Integration-based Near-Memory-Computing Architecture on HBM for Large-scale AI >

Ref) Jiwon Yoon, Teralab

< Twin Tower High Bandwidth Memory (HBM) with Near Memory Computing (NMC) Architecture for Large Memory Capacity and High Bandwidth System >

Ref) Taesoo Kim, Teralab

< L3 Cache Embedded GPU-High Bandwidth Memory
(L3E-GPU-HBM) Interposer Architecture for Large Language Model (LLM) >

Ref) Haeseok Suh, Teralab

< Level 3(L3) cache stacked GPU architecture with high bandwidth memory(HBM) for high performance in large language models(LLMs) >

Ref) Hyunah Park, Teralab 

< 3D Stacked Neural Processing Unit-System on Chip  (NPU-SoC) Architecture for Generative Artificial Intelligence >

Ref) Taesoo Kim, Teralab 

< 3-Dimensional (3D) System on Chip - Neural Processing Unit (SoC - NPU) Architecture for High Performance Computing (HPC) for Generative Artificial Intelligence (GAI) >

Ref) Jungmin Ahn, Teralab

< Memory-Centric Computing Architecture with Memory Coherent Interface >

Ref) Jiwon Yoon, Teralab

< Large-scale Chiplet Package on RDL Interposer with Local Silicon Bridge >

Ref) Jihun Kim, Teralab

< Specification of FWSC, WSE-2 of Cerebras >

Ref) Hyunwoo Kim, Teralab

< Cross-section view of the proposed hierarchical PDN structure for FWSC package >

Ref) Hyunwoo Kim, Teralab