Welcome to KAIST TERALAB
Research Area: Design Optimization of Through-silicon Via(TSV) using DNN for Noise Coupling Suppression
E-mail: keunwookim@kaist.ac.kr
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Research Area: SI, PI, EMC/EMI
E-mail: seyoung.jo@kaist.ac.kr
Research Area: Analysis of SI & PI using Machine Learning
E-mail: jihunkim@kaist.ac.kr
E-mail: joonsangpark@kaist.ac.kr
E-mail: seonguk@kaist.ac.kr
Research Area: Machine learning-based power distribution network design optimization.
E-mail: haeyeonkim@kaist.ac.kr
Research Area: SI, PI, EMI/EMC
E-mail: sungeun.lee@kaist.ac.kr
Research Area: Signal Integrity Design and Analysis of Processing-in-Memory Architecture based on High Bandwidth Memory
E-mail: jiwon.yoon@kaist.ac.kr
E-mail: junghyunlee@kaist.ac.kr
Research Area: AI-based GPU-HBM Architecture Design Considering SI, PI, and AI Workload
E-mail: haeseoksuh@kaist.ac.kr